The Problem Current computing architectures are designed for an old paradigm

From Supercomputers to Smartphones, energy efficency is paramount. The current #1 TOP500 system achieves only 5 GFLOPs/watt, while the next generation of HPC, or Exascale systems, require over a 10x improvement in energy efficency to be practical.

Simple CMOS scaling (usually thought of as Moore's law) is coming to an end, and existing technology paradigms will not be able to reach Exascale. The most optimistic estimates are predicting 25 GFLOPs/watt by the end of the decade, and 50 GFLOPs/watt by 2025.

All branches of computing have relied on the trickling down of innovation from the HPC industry, and stagnant designs that are 30+ years old are holding back the entire computing industry from achieving the goals of next generation computing systems.

*All FLOPs numbers are IEEE Double Precision (FP64)

The REX Neo Architecture

REX Computing is developing a new, hyper-efficient processor architecture targeting the requirements for the supercomputers of today, and all the computers of tomorrow.

To do this, we are throwing out the feature creep and bloat of processors of the past 30 years, and using improvements in the world of software to greatly simplify the processor itself to only what is necessary.

In doing so, we are able to deliver a 10 to 25x increase in energy efficiency for the same performance level compared to existing GPU and CPU systems

The Neo Chip

256 cores per chip, scratchpad memory, a 2D-mesh interconnect, and a revolutionary high bandwidth chip-to-chip interconnect achieve:

256 GFLOPs DP or 512 GFLOPs SP
at 64 to 128 GFLOPs/watt

  • Same performance for integer calculations.
  • Balanced memory bandwidth allows near-theoretical peak performance.
  • Extreme scalability: near limitless number of Neo chips per node.

Software and Development Tools

Hardware/Software codesign is a crucial component of the Neo architecture, and specific emphasis was given to give programmers both development ease and low-level access to the hardware to maximize efficiency and performance.

Portable Applications
  • Neo cores are capable of running a minimal Linux environment.
  • Targeting the MIMD Neo architecture can be as simple as cross-compiling existing code.
  • Compatible with existing IDEs and debugging tools.
Performance Tuning Suite
  • Compiler support for advanced automatic scratchpad management (integrated with GCC and LLVM).
  • Code profiling tools enable evidence-driven optimization.
Complete Control Over Hardware
  • Optional access to unique features, including explicit data flow management and static scheduling.


Thomas worked at the MIT Institute for Soldier Nanotechnologies for 3 years as both an end user of HPC systems, and later transitioned into designing and building them at the lab. This experience led to starting REX Computing in 2013 as a recipient of Peter Thiel’s “20 Under 20” Fellowship, where he leads architectural design and operations. Thomas has been featured on Forbes’ 30 under 30 list and is a project lead for the Open Compute Project HPC Group.


Paul started programming as a child, and studied CS at Georgia Tech. He has worked in fields including structural biology, theoretical ecology, and nanofabrication. Paul was part of the 2012 class of Thiel Fellows, where he founded a synthetic biology startup and worked at Lawrence Berkeley National lab for 18 months. He later joined Thomas in starting REX, where he contributes an extensive knowledge of low level software and tool development


Our Advisors

Board of Advisors

  • Bill Boas: Chairman, System Fabric Works; former Director, Cray; former Advanced Architectures Team, Lawrence Livermore National Lab

  • Kevin Moran: CEO, System Fabric Works.

Technical Advisory Board

  • John Gustafson: CTO, Ceranovo; former Director of eXtreme Technologies Lab, Intel; former Chief Product Architect, AMD.

  • Raghuram Tupari: Former Corporate VP - Silicon Design AMD.

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