The Problem Processor architectures have not been rethought for over 25 years, and the end of CMOS scaling will make it increasingly difficult for performance and efficency improvements without a fresh design.

Existing processor architectures were designed in a time where the amount of energy to move data was roughly equal to the amount of energy required to do useful computation with that data.





Energy cost for performing a 64 bit FLOP (In picojoules)

Moving 64 bits from memory takes over 40x more energy than the actual double precision floating point operation being performed with that data.



REX Computing is rethinking the traditional hardware managed cache hierarchy, and in removing unnecessary complexity, is able to significantly reduce power consumption and total area.

The REX Neo Architecture


REX Computing is developing a new, hyper-efficient processor architecture targeting the requirements for the supercomputers of today, and all the computers of tomorrow.


To do this, we are throwing out the feature creep and bloat of processors of the past 30 years, and using improvements in the world of software to greatly simplify the processor itself to only what is necessary.



In doing so, we are able to deliver a 10 to 25x increase in energy efficiency for the same performance level compared to existing GPU and CPU systems

The Neo Chip


256 cores per chip, scratchpad memory, a 2D-mesh interconnect, and a revolutionary high bandwidth chip-to-chip interconnect achieve:


256 GFLOPs DP or 512 GFLOPs SP
at 64 to 128 GFLOPs/watt

  • Same performance for integer calculations.
  • Balanced memory bandwidth allows near-theoretical peak performance.
  • Extreme scalability: near limitless number of Neo chips per node.

Software and Development Tools


Hardware/Software codesign is a crucial component of the Neo architecture, and specific emphasis was given to give programmers both development ease and low-level access to the hardware to maximize efficiency and performance.

Portable Applications
  • Neo cores are capable of running a microkernel/RTOS with scheduling and memory abstraction.
  • Targeting the MIMD Neo architecture can be as simple as cross-compiling existing code.
  • Compatible with existing IDEs and debugging tools.
Performance Tuning Suite
  • Compiler support for advanced automatic scratchpad management (integrated with GCC and LLVM).
  • Code profiling tools enable evidence-driven optimization.
Complete Control Over Hardware
  • Optional access to unique features, including explicit data flow management and static scheduling.

About


Thomas worked at the MIT Institute for Soldier Nanotechnologies for 3 years as both an end user of HPC systems, and later transitioned into designing and building them at the lab. This experience led to starting REX Computing in 2013 as a recipient of Peter Thiel’s “20 Under 20” Fellowship, where he leads architectural design and operations. Thomas has been featured on Forbes’ 30 under 30 list and is a project lead for the Open Compute Project HPC Group.



 

Paul started programming as a child, and studied CS at Georgia Tech. He has worked in fields including structural biology, theoretical ecology, and nanofabrication. Paul was part of the 2012 class of Thiel Fellows, where he founded a synthetic biology startup and worked at Lawrence Berkeley National lab for 18 months. He later joined Thomas in starting REX, where he contributes an extensive knowledge of low level software and tool development

 

Our Advisors


  • John Gustafson: CTO, Ceranovo; former Director of eXtreme Technologies Lab, Intel; former Chief Product Architect, AMD.


  • Bill Boas: Chairman, System Fabric Works; former Director, Cray; former Advanced Architectures Team, Lawrence Livermore National Lab


  • Kevin Moran: CEO, System Fabric Works.

press


Moving data on a chip can take 40 times more energy than to compute that same amount of data. It also slows things down. So by tweaking the memory to make it less locked down in the hardware, REX is saving energy and boosting speed.
The company recently received $1.25 million in funding from Founders Fund, a venture capital firm cofounded by Peter Thiel.
The result of his research is an up and coming chip called Neo, which brings to bear a new architecture, instruction set, and core design and if assumptions are correct, can do this in a power envelope and performance target that goes beyond the current requirements for exascale computing goals.
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